Dr. H.R.Bhagyalakshmi

10.13

Name of Teaching Staff

Dr. H.R. Bhagyalakshmi

 

 

Designation

Associate Professor

 

Department

Electronics & Communication Engineering

 

Email ID

hrbhagya.ece@bmsce.ac.in

 

Date of Joining the Institution

October, 1988

 

Qualifications with Class/Grade

UG

PG

PhD

BE –

First Class

ME –

First Class

Awarded

 

Total Experience in Years

Teaching

Industry

Research

28 years

-

-

 

Papers Published

National

International

3

11

 

Papers Presented in Conferences

National

International

3

5

 

PhD Guide? Give field & University

Field

University

Low Power Digital Electronics

VTU

 

PhDs / Projects Guided

PhDs

Projects at Masters level

Guiding – 2 Scholars

-

 

Books Published / IPRs/ Patents

-

 

Professional Memberships

ISTE

 

Consultancy Activities

-

 

Awards

-

 

Grants fetched

-

 

Interaction with Professional

Institutions

-

Publications

International Journals

1. H R Bhagyalakshmi, M K Venkatesha, “Optimized reversible BCD adder using new

reversible logic gates”, Journal of Computing, Volume 2, Issue 2 , February 2010.

2. H R Bhagyalakshmi, M K Venkatesha, “Improved design of a Multiplier using reversible

logic gates”, International Journal of Engineering Science and Technology, Volume 2(8),

3838-3845, August 2010.

3. H R Bhagyalakshmi, M K Venkatesha, “Optimized design of BCD adder and Carry skip

BCD adder using reversible logic gates”, International Journal of Computer Science and

Engineering, Volume 3(4), 1439-1449, April 2011.

4. H R Bhagyalakshmi, M K Venkatesha, “Design of a Multifunction BVMF Reversible

Logic Gate and its Applications”, International Journal of Computer Applications,

Volume 32, 36-41, October 2011.

5. Sudharshan M, H R Bhagyalakshmi, M K Venkatesha, “Novel Design of one digit high

speed Carry select BCD subtractor using Reversible logic gates”, International Journal

of Emerging Technology and Advanced Engineering, Volume 2, Issue 7, July 2012.

6. Prathibha Rani T R, H R Bhagyalakshmi, M K Venkatesha, “Optimized Reversible carry

select BCD adders using Reversible logic gates”, International Journal of Computer

Technology and Applications, Volume 3 (4), 1550-1556, July-August 2012.

7. H R Bhagyalakshmi, M K Venkatesha, “Optimized multiplier using reversible multi

control input Toffoli gates” , International Journal of VLSI design and Communication

Systems (VLSICS), December 2012.

8. Rakshith Saligram, Shrihari Shridhar Hegde, Shashidhar A. Kulkarni, H. R. Bhagyalakshmi,

M. K. Venkatesha: Design of Parity Preserving Logic Based Fault Tolerant Reversible

Arithmetic Logic Unit. April 2013

9. “Design and Implementation of GPIO Enumeration Library and Application for UEFI-

BIOS”, Srividya G Kedlaya, H R Bhagyalakshmi, International Journal of Scientific

Engineering and Technology, (ISSN : 2277-1581), Volume No.3 Issue No.5,

pp : 524-528 , 1 May 2014.

10. “Noise Analysis of Current -Mode Preamplifier Circuit ” , Prasanth. N, Likhith B P, Naveed

Anjum, Gajendra K A, H R Bhagyalakshmi, Int. Journal of Engineering Research and

Applications , ISSN : 2248- 9622, Vol. 4, Issue 5, Version 3, pp. 91-94, May 2014.

11. “Programmable Current Gain CMOS Amplifiers” , Prasanth. N, Likhith B P, Naveed

Anjum, Gajendra K A, H R Bhagyalakshmi, International Journal of Engineering Research

& Technology (IJERT), ISSN: 2278-0181, Vol. 3 Issue 5, May 2014.


International Conferences:

12. H R Bhagyalakshmi, M K Venkatesha, “Optimized error detection circuit using new

reversible logic gates” , April 21-23, 2010, held at ICSE-2010 at DSCE, Bangalore.

13. H R Bhagyalakshmi, M K Venkatesha, “Toffoli cascade synthesis of an optimized

two-bit comparator” , ICERCT-2012, P E S College of Engineering, Mandya,

December 21- 23, 2012 published in Springer - Lecture Notes for Electrical

Engineering – LNEE

14. Asha Nair S , H R Bhagyalakshmi, “ Customizing TAP Design for Intel’s Next

generation Chips”, International Conference on Information and Communication

Engineering, ISBN:978-81- 31703-83- 2, 28 th June, 2013, Bangalore

15. “Program outcome attainment through course outcomes: A Comprehensive approach”,

H R Bhagyalakshmi, D Seshachalam, S Lalitha, International conference on

Transformations in Engineering education (published by Springer), Hubli, January 2014.

16. “Student performance using Blooms cognition levels: A case study”, H R

Bhagyalakshmi, D Seshachalam, ICTIEE-2015, B M S College of Engineering,

Bangalore, January 2015.

17. “Continuous Improvement in the Assessment Process of Image Processing Course”,

Lalitha S, Bhagyalakashmi H R , Harishanand K S, ICTIEE-2015, B M S College of

Engineering, Bangalore, January 2015.

18. “A case study: Improved learning through course assessment “,H R Bhagyalakshmi,

D Seshachalam, Ajaykumar Devarapalli, ICTIEE-2015, B M S College of Engineering,

Bangalore, January 2015.

National Conferences:

19. Lavakumar, H R Bhagyalakshmi, M K Venkatesha, “Optimized Multiplier Using 4x4

Reversible Logic Gates”, National Conference in Networking, Embedded and Wireless

Systems, NEWS-2010, BMSCE, August 2010, Bangalore.

20. Prathibha Rani T R , H R Bhagyalakshmi, M K Venkatesha, “Optimized 1-digit

Carry select BCD adder using reversible logic gates”, National Conference in

Networking, Embedded and Wireless Systems NEWS-2012, BMSCE, August

2012, Bangalore.

21. Srividya G Kedlaya, H R Bhagyalakshmi , M K Venkatesh, “Design and

implementation of 16 X 16 bit Vedic Multiplier”, Proceedings of National Conference

on Wireless Communication, Signal Processing, Embedded Systems-WISE 2013