Dr. Vasundara Patel K S

Name of Teaching Staff

Dr. Vasundhara Patel K S

Designation

  Professor

Department

Electronics & Communication Engineering

Email ID

vasu.ece@bmsce.ac.in

Date of Joining the Institution

06-10-1999

Qualifications with Class/Grade

UG

PG

PhD

 

 

I Class

Distinction

In Electronics Engineering

Total Experience in Years

Teaching

Industry

Research

 

 

19

3

10

Papers Published

National

International

 

 

 

20 journal publications

 

Papers Presented in Conferences

National

International

 

 

12

30

PhD Guide? Give field & University

Field

University

 

 

VLSI

VTU

PhDs / Projects Guided

PhDs

Projects at Masters level

 

 

Guiding-4

40

Books Published / IPRs/ Patents

Patent Applied: Invention Titled “Method and System for Arithmetic Circuits in quaternary Logic.

 

Professional Memberships

IEEE, IMAPS India, ISTE, IACSIT

Consultancy Activities

-

Awards

Best Student research papers

1.“Low power D flip-flop using non-classical logic”, in 12th ISTE State Level Students Annual Convention on Convergence of Science and Engineering in Education & Research – A National perspective.  

2.“One bit Quaternary ALU” in 13th ISTE State Level Students Annual Convention on Convergence of Science and Engineering in Education & Research – A National perspective.

3.“Frequency and Time Domain Analysis of High Resolution Sigma-Delta ADC”, in National Conference on Networking, Embedded and Wireless Systems, NEWS-2012, BMSCE,

4.  “Implementation of 5-32 Address decoders for SRAM Memory in 180nm Technology”, at International conference on Electrical electronics Communications, Computer technologies Optimization techniques (IC EE CC OT)-2017

Grants fetched

TEQIP-2 funds (10 Lakhs) for Synopsis Software tools  and ESSCI equipment facility for  VLSI Labs

15 lacks funds from ESSCI

Interaction with Professional

Institutions

IISc, India Electronic Semiconductor Association, Electronic Sector Skill Council of India.

Details of Publication:

 

 

Paper presented Abroad

 

1.Vasundara Patel K S, Dr K S Gurumurthy  Quaternary CMOS Combinational Logic Circuits”, has been presented in IEEE International conference on semiconductor technology in conjunction with ICIMT 2009, on 18 - 19, December 2009, Jeju Island, South Korea.

2.Vasundara Patel K S, Dr K S Gurumurthy Moving from binary towards multi-valued logic logic”, has been presented in International conference, WORLD COMP 2009, on 13 - 16, JULY, Las Vegas, Nevada, USA

3. Satish Masthenhally Nachappa, Jeevitha A S, Dr.Vasundara Patel K S “Comparative Analysis of Digital Circuits using 16nm FinFET and HKMG PTM Models”, has been presented in IEEE International conference, 2018 Future of Information and Communication Conference (FICC). Singapore,

 

International Journal Papers

 

1.Poornima Baliga M, Vasundhara Patel K S, “A Design Implementation of Single Stage Amplifiers using HEMT Technology”, International Research Journal of Engineering and Technology (IRJET), e-ISSN: 2395 -0056, Volume: 04 Issue: 01 | Jan -2016,  www.irjet.net,  p-ISSN: 2395-0072, © 2017, IRJET | Impact Factor value: 5.181 | ISO 9001:2008 Certified Journal | Page 105 to 110

 

2.Srinivas Aynapure Dr. K S Vasundara Patel,Hard systematic Error-Correcting Codes for Matching of Data using Low-Complexity Low-Latency Architecture” International journal of Electrical, Electronics and Computer Science Engg. E-ISSN: 2348-2273 // P-ISSN p: 2454 – 1222, Special Issue, NEWS 2016,  03-04 JUNE page:190 to 193

 

3.Varsha S R, Dr. K S Vasundara Patil, “Schmitt Trigger Based SRAM Using CNTFET Technology”. International journal of Electrical, Electronics and Computer Science Engg. E-ISSN: 2348-2273 // P-ISSN p: 2454 – 1222, Special Issue, NEWS 2016,  03-04 JUNE. Pages 175 to 176

 

4.Namratha patil, Dr. Vasundara patel, Prabhu Bhairi, SeviTech Systems Private Limited, “Reconfigurable NoC For IOT Based SOCs”, International journal of Electrical, Electronics and Computer Science Engg. E-ISSN: 2348-2273 // P-ISSN p: 2454 – 1222, Special Issue, NEWS 2016,  03-04 JUNE. Page 204 to 206

 

5.Inayathulla khan, Vasundhara Patel K S, “Implementation of an efficient floating point multiplier using Karatsuba and Urdhva - Tiryagbhyam algorithm” International journal of Electrical, Electronics and Computer Science Engg. E-ISSN: 2348-2273 // P-ISSN p: 2454 – 1222, Special Issue, NEWS 2016,  03-04 JUNE. page:183 to 186

 

6.Tarun Kumar Nagori, Dr. Vasundara Patel K S, “ROBUST AND RECONFIGURABLE VERIFICATION PLATFORM FOR NOC IN IOT SOC DESIGN”,  International Journal of Emerging Technologies and Innovative Research, ISSN: 2349-5162 | Impact Factor: 4.14, August 2016, Volume 3, Issue 8, pages 16-17

 

7. N. Roopa, Dr. Vasundara Patel K S, “Implementation of QPSK Modulator Using Direct Conversion Method”, IJSRD - International Journal for Scientific Research & Development| Vol. 4, Issue 06, 2016 | ISSN (online): 2321-0613, pp 1048 to 1050

 

8.Phanindra L S, Rajath MN, Rakesh V,  Vasundara Patel K S, Novel Design of Multiple-Valued Static Memory Array using CNTFET Technology”,   International journal of Electrical, Electronics and Computer Science Engg. E-ISSN : 2348-2273 // P-ISSN p : 2454 – 1222, Special Issue, NEWS 2016, 03-04 JUNE. Pages 136 to 141

 

9.Rajagopal A, Karibasappa. K, Vasundara Patel K S, “FPGA Implementation of a Modified Turbo Encoder”,   April 2015, International Journal of Computer Applications (2250-1797) IMPACT FACTOR: 3.12, Volume 116 – No. 6, Page No.  27 – 29

 

10. Vasundara Patel K. S., Harsha N. Bhushan, Kiran G. Gadag, Nischal Prasad B. N., Mohmmed Haroon, “Schmitt Trigger Based SRAM Using Finfet Technology- Shorted Gate Mode”, World Academy of Science, Engineering and Technology, International Journal of Computer, Electrical, Automation, Control and Information Engineering Vol:8, No:2, 2014, scholar.waset.org/1999.4/9998646, pages 383 to 386.

 

11.Priyanka P,  Vasundara Patel K S, “Design Implementation of High-performance Logic Arithmetic Full Adder Circuit based on FinFET 16nm Technology”,   April 2015, International Journal of Science and Research (IJSR) ISSN (Online): 2319-7064 Index Copernicus Value (2013): 6.14, Impact Factor (2013):4.438, Paper ID: SUB152908 490, Volume 4, Issue 4, Page No.490-494.

 

International IEEE conference paper

 

1.Rajagopal a, Karibasappa k, Vasundara patel k. s. “FPGA implementation of logarithm of a number to base 2”, 2017 International Conference on Innovative Mechanisms for Industry Applications (ICIMIA), Dayananda Sagar College of Engineering, 21 Feb - 23 Feb 2017,

 

 

  2.Rajagopal A, Karibasappa. K, Vasundara Patel K S, “Design of SPA decoder for CDMA applications”,  IEEE International Conference on Intelligent Computing and Control (I2C2), 2017, 23-24 June 2017, INSPEC Accession Number: 17650820, DOI: 10.1109/I2C2.2017.8321793, Conference Location: Coimbatore, India

 

3.Phanindra L S, Rajath MN, Rakesh V,  Vasundara Patel K S, A Novel Design and Implementation of Multi-Valued Logic Arithmetic Full Adder circuit using CNTFET,   2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT),  Date of Conference: 20-21 May 2016, Date Added to IEEE Xplore: 09 January 2017. INSPEC Accession Number: 16583171, DOI: 10.1109/RTEICT.2016.7807885.

 

4.Shanmukha Sandesh, Niranjan S, Samanvitha B Bhargav, Sneha B, Vasundara Patel K S, “A novel architecture implementation in RF Amplifier using CMOS 180nm technology”,June 2015, IEEE International Int. Conf. Advance Computing Conference (IACC), 2015, vol., no., pp.1185,1190, 12-13 doi: 10.1109/IADCC.2015.7154890

 

5. G. N. Sowmya, K. S. Vasundara Patel, Rajani Rao “Modeling of Sigma-Delta ADC with High Resolution Decimation Filter”, International Joint Conference on Advances in Signal Processing and Information Technology, SPIT 2012, 20-21 September, Dubai, United Arab Emirates,  pp 95-100,  Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 117. Springer.

 

6.Vasundara Patel K S, Dr K S Gurumurthy, “Design of High performance Quaternary adder” IEEE International Symposium on MVL, Finland, May 23rd to 25th, 2011

 

7.Varun A V, Vinay Sheshadri, Shivaramakrishnan R, Vasundara Patel K S “Design and complexity analysis of Reed Soloman Code algorithm for advanced RAID system in quaternary domain”, IEEE International Symposium on Very Large Scale Integration (ISVLSI 2011), July 4 – 5, IIT Chennai.2011.

 

 

  1. Rajagopal A, Karibasappa. K, Vasundara Patel K S "Study of LDPC decoders with Quadratic residue sequence for Communication System". Accepted for Indersceince journal.