Name of Teaching Staff






Electronics & Communication Engineering

Email ID


Date of Joining the Institution


Qualifications with Class/Grade




FIRST class



Total Experience in Years




19 + years



Papers Published





Papers Presented in Conferences





PhD Guide? Give field & University





PhDs / Projects Guided


Projects at Masters level



Books Published / IPRs/ Patents


Professional Memberships


Consultancy Activities



1.  Best paper award for the paper titled “Implementation of power optimized High speed flipflop” in the national conference (NEWS 2010) conducted by BMS college of Engineering, Bangalore


2.  Best paper award for the paper titled “A Novel technique for implementation of latch and flip-flop” in the national conference conducted by New Horizon college of Engineering, Bangalore.


 3.  Best teacher award for the year OCT’ 98 in Vellore Engineering college (now Vellore Institute of Technology), Vellore.


4. UG student project Guided by me titled “HAND TALK USING FLEX SENSORS WITH VOICE INDICATION - ASSISTIVE TECHNOLOGY FOR THESPEECH AND HEARING IMPAIRED” has won special seminar prize of “PROJECT OF THE YEAR-KARNATAKA” award during the Seminar and Exhibition of Student Projects – 35th SERIES, SPP: 2011-12held on 13th and 14th July 2012 conducted by IISc, Bangalore.


5. UG student project Guided by me, titled as “Low Power Pipelined FFT Processor Using self timed Adder” has won WINNER  AWARD in the All India level Cadence Design Contest-2012 conducted by Cadence India Pvt Ltd, India. http://www.indiatechonline.com/it-happened-in-india.php?id=875


6. UG student project Guided by me, titled as “Implementation of Low Power Pipelined VLSI Architecture for Mixed Bio Signal lossless Compressor using GRHF Coding Algorithm” was in the Top-7 of the Bachelor’s category –All India Level Cadence Design Contest 2013.

Grants fetched


Interaction with Professional


  1. Reviwer for 47th All India Student Design Competition, 2016, student projects organized by NDRF, Institution of Engineers (India)
  2. Advisory and Technical Committee member in the National Conference on Recent Trends & Applications in Electrical & Electronics Engineering, NCRTAEEE -2016 & 2017.organised by KSIT in association  with VTU, IEEE and ISTE.

Details of publications


  1. Shruti K, R. Jayagowri, “VLSI Architecture of Colour Interpolation Processor for Real Time Video Application Using Adaptive Edge Enhancement Technique”, International Journal of Electrical Electronics & Computer Science Engineering Special Issue – June 2016 -NEWS 2016 | E-ISSN : 2348-2273 | P-ISSN : 2454-1222, pp130-135,  P Impact Factor (2016) :3.952
  1. Kiran JP, Dr. R Jayagowri, “Abstract, Correct by Construction and Faster Register Modeling of AMBA APB Bus”, International Advanced Research Journal in Science, Engineering And Technology in Vol. 3, Issue 8, August 2016, pp 103-105, DOI 10.17148/IARJSET.2016.3818, ISSN (Online) 2393-802, ISSN (Print) 2394- 588. Impact factor (SJIF Evaluated) 2015: 3.943
  2. R. Jayagowri , “Techniques for Low Power and Area Optimized VLSI Testing using Novel Scan Flip-Flop” published in International Journal of Computer Applications(IJCA) (0975 – 8887), Vol. 113 , No. 5, March 2015, pp 22- 28. ISBN : 973-93-80885-52-9. Impact factor 2014: 0.715.
  3. Vinay S, pramod K. P, R. Jayagowri, S. Ranjana & priyanka V, “ Implementation of Low Power VLSI Architecture for Lossless Compressor and Decompressor”, published in International Journal of Electronics and Communication Engineering(IJECE), ISSN(P): 2278-9901; ISSN(E): 2278-991X, Vol. 2, Issue 5, Nov 2013, pp 205-212.Impact factor(JCC): 3.2029
  4. R. Jayagowri, karthik.S.Rao, Karthik.C.V, Keshava Koushik.S , “Design and Implementation of Low-Power Pipelined FFT Processor”, Published in International Journal of VLSI & Signal Processing Applications, ISSN 2231-3133, Vol-2, Issue- 4,pp 330-335.
  5. R. Jayagowri and K. S. Gurumurthy,  “Power Optimization during Shift Cycle of Scan based IC Testing “,published in the International Journal of Recent Trends in Engineering, by the Academy Publishers, Finland, ISSN 2158-5555, Vol.4, No.3, Nov 2010, pp 135-138.
  6. R. Jayagowri and K. S. Gurumurthy, “Design and Implementation of Area and Power Optimized Novel Scan flop”, published in International journal of VLSI Design & Communication Systems (VLSICS), ISSN 0976 – 1357, Vol.2, No.1, March 2011, pp.37-43. Academic Resources Impact factor:4


  1. R. Jayagowri and K. S. Gurumurthy, Gating Technique with Modified Scan Flip-flop for Low Power Testing of VLSI Chips,  VLSI Design and Test Symposium (VDAT’12), July 2012, Springer LNCS 7373, pp(52-58).
  2. Jayagowri, R., Gurumurthy, K.S : A Technique for Low Power Testing of VLSI Chips. In: Proceedings of IEEE International Conference on Devices, Circuits and Systems, IEEE DOI: 10.1109/ICDCSyst.2012.6188654, pp. 662 – 665, March 2012, pp.661-664.
  3. Jayagowri, R., Gurumurthy, K.S : A Review on testing of 3D ICs.,      In proceedings of International conference on VLSI & Signal processing (ICVSP-12),ISBN 978-81-7286-723-2,4-5 May2012, pp. 41-45.
  4. Jayagowri,R., Shivaprasad B, Srikanth K G : Design of an Efficient D Flip-Flop with Low Power Dissipation and Less Transistor Count, In proceedings of International conference on VLSI & Signal processing (ICVSP-12),ISBN 978-81-7286-723-2,4-5 May2012, pp. 18- 21.
  5. Shibani Nataraj, Vinay S, Jayagowri, R.,: A Proposed Clock Blocking Cell in Sequential Circuits, In proceedings of International conference on VLSI & Signal processing (ICVSP-12),ISBN 978-81-7286-723-2,4-5 May2012, pp. 22- 25.
  6. Jayagowri, R., Gurumurthy, K.S: An Area Optimised Combined Passtransistor and CMOS based method to implement Latch and Flip-Flop., In proceedings of International conference on Information Communication & Embedded Systems,24-25 February 2012organised by S. A. Engineering college, in association with IEEE Chennai chapter, Technical Journals, Computer Society of India.
  7. Paper titled as “Power Optimization during Shift Cycle of Scan based IC Testing”, is published in International Joint Journal Conference in Computer, Electronics and Electrical, CEE 2010conducted on 24-25 November-2010.
  8. Jayagowri, R., Gurumurthy, K.S: “Power and delay Optimized sequential circuit for VLSI Testing” International Conference on COMMUNICATION COMPUTATION CONTROL & NANOTECHNOLOGY (ICN-2010) October 29 –30,2010 Organized by Departments of Telecommunication Engineering, Electronics & Communication Engineering and Instrumentation Technology, RURAL ENGINEERING COLLEGE, BHALKI-585328.
  9. Jayagowri, R.: “ Low power CMOS Technique implementation for real time image processing architecture”, International conference on  emerging micro electronics and interconnection technology, EMIT-08, conducted by IMAPS India chapter between December 15th to 18th 2008.


  1. Shruti K, R. Jayagowri, “VLSI Architecture of Colour Interpolation Processor for Real Time Video Application Using Adaptive Edge Enhancement Technique”,NEWS-2016
  2. Jayagowri, R., Shibani Natraj, Shivaprasad:, “Reduction of power dissipation in a memory element”, in national conference on Advances in Electronics and Intelligent computing-2011 on 2nd May 2011 conducted by East west Institute of Technology, Bangalore.
  3. Jayagowri, R., Gurumurthy K S ,“Power optimized high speed flip flop in the national conference on Networking , Embedded and wireless systems”, (NEWS- 2010), conducted on 6th August – 2010, organized by Department of ECE, BMS College of engineering Bangalore.
  4. Jayagowri, R., Gurumurthy K S :“ A Novel technique to implement the latch and FF”, in the National conference on Recent  advances in electronics and communication on 21st may 2010 organized by department of Electronics and Communication, New Horizon college of engineering, Bangalore.
  5. Jayagowri, R., Karthik: “power optimized combinational circuit’, in the 4th National conference on advances in information technology, NCAIT – 2010,held on 8th may 2010, organised by Dept of Information science and engineering, SJB Institute of technology, Bangalore
  6. Jayagowri, R., Anitha:, “A novel VLSI architecture for image scaling in the 4th National conference on recent trends in communication electronics and information technology, NACTECIT 10, held on April 23-24. 2010 organised by CMRIT, Bangalore. Sponsored by ISRO, ministry of defence, ISTE, wiley publisher.
  7. Jayagowri, R., A. Abhishek, K. Chaitanya kumar: “power optimization in RTL Level” in the National conference on challenges in micro /Nano electronics conducted by IMAPS India Chapter and SIT, Tumkur on March 26-27, 2010.
  8. Jayagowri, R., C. Meena: “ Power efficient technique for C & S unit  in image processing Architecture”, National conference on VLSI organised by TPGIT, vellore, Anna university on 12th August 2006.
  9. Jayagowri, R., Dr. N. Kumaravel: “Feature clustering and labeling for video object segmentation using ANN,” National conference on emerging trends in engineering and technology, conducted by Dr. M.G.R educational and research institute, Deemed University, between May 1 – May3, 2004.
  10. Jayagowri, R.: “ A view of telemedicine ECG, Blood pressure” in National Seminar electronics advances and trends conducted by Arunai engineering college between January 23 January 24, 2000
  11. Jayagowri, R., Dr. K. Chidambaram:  “Optics a tool for biomedical engineering”, National Seminar on Bio-medical engineering. The Indian scenario 12th march – 13th march 1999. Organised b center for Bio medical engineering, Vellore Engineering College, between 12th & 13th March 1999.